The present invention generally relates to an integrated circuit, and more particularly, to a decoupling capacitor for use in an integrated circuit.
The extremely rapid switching rates of the discrete components that make up integrated circuits typically cause current transients in the power buses of the integrated circuits. These current transients may last for several nanoseconds. Unfortunately, for a given integrated circuit, the typical power supply driving the power bus requires an order of magnitude in the microsecond range to compensate for the current transients injected on the power bus by the discrete components. Moreover, the reduction in gate threshold voltage of the various discrete components in the integrated circuit requires the power bus to deliver a stable voltage signal having a minimum of voltage level variation. Consequently, power bus stability, in terms of current response and voltage level fluctuation, is a significant issue in the design of an integrated circuit.
The conventional approach to provide power bus stability is the insertion of decoupling capacitors between the power bus and the one or more discrete components. However, the technical evolution of these discrete components has continued to realize a downwards scale to achieve density, speed and power improvements in the art of integrated circuit technology. With the development of new integrated circuit technologies and structures, the discrete devices forming the integrated circuit often have submicron structural dimensions. For example, in the field of metal oxide semiconductor field effect transistors (MOSFETs) the structure and design of MOSFET""s continue to realize an ever shorter channel length between the source region and drain region of the MOSFET. The result of the trend toward ever shorter channel lengths yields a device that is easier to switch. Nevertheless, the gate oxide thickness of the device is merely a few layers of atoms and is approaching fundamental limits. For example, in a 0.11 micron complimentary metal-oxide-semiconductor (CMOS) device, the gate oxide electrical thickness is often less than two nanometers. Consequently, the reduced gate oxide thickness of a 0.04 micron CMOS short channel device makes the device prone to the effects of gate leakage current from other devices coupled thereto. One example is gate tunneling leakage current generated by one or more decoupling capacitors that couple the device to the power bus.
Although the decoupling capacitor plays a significant role in providing power bus stability, it is also a significant contributor of gate leakage current in the integrated circuit, which, in turn, contributes to an increased channel charge in the 0.11 micron device. Consequently, the increased channel charge in the 0.11 micron device diminishes the control that the device""s gate and body terminals have on the channel.
Decoupling capacitor leakage current is attributable to the thin gate oxide thickness of the decoupling capacitor, that is, a gate oxide electrical thickness of two nanometers or less. Although the leakage current associated with decoupling capacitors is burdensome, it is undesirable to increase the gate oxide thickness of the 0.11 micron CMOS device so as to increase the gate threshold voltage (VT) of the device to lower the portion of the channel charge contributed by the source body and drain body of the device because, the increase in the gate oxide thickness allows for an increase in electrostatic effects on VT and significantly slows switching speed of the device.
The present invention addresses the above-described limitations of a decoupling capacitor having a gate oxide layer electrical thickness of two nanometers or less. The present invention provides an approach to enable the use of a metal-oxide-silicon (MOS) capacitor having a leakage current value suitable for use with 0.11 micron CMOS technology and with CMOS technology beyond 0.11 microns, for example 0.09 micron technology.
In one embodiment of the present invention, a decoupling capacitor having a transistor gate leakage current suitable for use with one or more MOSFET""s having a channel length of about 0.04 microns or less is provided. The decoupling capacitor includes a gate oxide region of sufficient thickness to yield an average off state leakage current (IOFF) between drain and source (IDS) of the capacitor of about 0.1 nA/xcexcm or less. The decoupling capacitor is also capable of providing an IOFF leakage current between the drain and gate (IDG) of about 0.02 nA/xcexcm, or less.
The above described approach benefits an integrated circuit that utilizes 0.11 micron CMOS technology so that the detrimental effects of leakage current previously contributed by one or more decoupling capacitors is significantly abated. As such, devices subject to more stringent leakage current requirements, for example, dynamic memory devices, can benefit from the 0.11 micron CMOS technology while maintaining stringent leakage current requirements.
In accordance with another aspect of the present invention, a method is performed in an integrated circuit comprising one or more CMOS devices having a channel length of about 0.04 microns or less to minimize leakage current from a decoupling capacitor coupled between the one or more CMOS devices and a power bus of the integrated circuit. By increasing a gate oxide layer thickness of the decoupling capacitor, gate tunneling current associated with the decoupling capacitor is minimized. Having increased the gate oxide layer thickness of the decoupling capacitor, the method then provides the steps of coupling a gate element of the decoupling capacitor to a voltage node capable of supplying a supply voltage value of about VDD. The method also provides the steps of coupling a source element of the decoupling capacitor to a voltage node or voltage source having a voltage potential of zero volts or less and coupling a drain element of the decoupling capacitor to a voltage node or voltage source having a voltage potential of about zero volts or less.
The above described approach benefits a microprocessor architecture that utilizes CMOS devices having a channel length of about 0.04 microns or less. Because of the increased thickness of the decoupling capacitors gate oxide region, the detrimental effects of leakage current from the capacitor on the CMOS devices are minimized and in some instances eliminated. As such, noise immunity of dynamic logic circuits within the microprocessor is not degraded and in fact is possibly enhanced.
In a further aspect of the present invention, an integrated circuit is provided having a 0.11 micron CMOS device and a decoupling capacitor coupled between the CMOS device and a power bus of the integrated circuit. The decoupling capacitor having a thick gate oxide region to minimize leakage current in the decoupling capacitor. The thick gate oxide region of the decoupling capacitor has an oxide electrical thickness of between about 2.7 nanometers and about 3.3 nanometers.
The above described approach allows an integrated circuit that utilizes 0.11 micron CMOS devices to avoid the effects of leakage current associated with one or more decoupling capacitors in either their on-state or off-state and thus avoid an increase in leakage power consumption of the integrated circuit. As such, overall power consumption of the integrated circuit is reduced, which, in turn, provides an integrated circuit having an improved thermal profile.
In yet another aspect of the present invention, a method is practiced in a microprocessor having one or more 0.11 micron CMOS devices for reducing leakage power in the microprocessor. The method includes the steps of inserting one or more decoupling capacitors having a thick gate oxide region into one or more decoupling capacitor locations in the microprocessor and coupling each of the inserted decoupling capacitors between a power bus of the microprocessor and the one or more 0.11 micron CMOS devices. The insertion of the decoupling capacitors having the thick gate oxide region provides the microprocessor with the capability to realize the reduced leakage power.
As a consequence of the above described approach, the leakage current associated with the coupling capacitors is minimized so that the stability and reliability of synchronous random access memory (SRAM) cells within the microprocessor are not compromised.